Verilog/rtl/ddc/db read in
Design Environment
synthesis env 變數設定
search_path
target_library (standard cell library)
link_library (standard cell library, macro lib , sram lib, design ware library, wireload model)
global synthesis var (icg type/)
operating condtion setting
donot use cell
I/O port attributes
drive strength of input port capacitive loading of output port
Design Constraints
Clock signal specification
period
duty cycle
transition time
skew
Delay specifications
maximum
minimum
Timing exception
false path
multicycle path
Path grouping
compile
report
